There are a variety of competing modulation techniques for wideband communications, including, for example, Phase Shift Keying (PSK), Amplitude Shift Keying (ASK), Quadrature Amplitude Modulation (QAM), and variations of each, to name a few. There is an increasing need for communication transmitters and receivers that can process and code/decode more than one modulated waveform. For example, various U.S. Government agencies communicate using Common Data Link Class 1 category A and B waveforms, Terrestrial Line of Sight waveform, classified direct downlink waveform, numerous waveforms for civil and military communications with satellites and/or military assets, and the (to be determined) commercial teledesic waveform. Overlap between these agencies, and between arms of other governments or multinational corporations that communicate over numerous disparate systems, is driving a need for flexible-modulation hardware that can operate among various communications waveforms such as those above. One approach in achieving the above hardware flexibility is a modem that is programmable for a variety of modulation schemes. Such a modem is termed a programmable digital modem, which falls within the class of software-defined radios.
Traditional pulse shaping is followed by interpolation by some integer factor, and is shown in block diagram form at FIG. 1A. Data input into an upsampling filter 11 at a symbol rate Rsymbol is upsampled by a factor of U, wherein U is an integer. The output from the upsampling filter 11 is then URsymbol, which is passed through a low pass filter 13 and input into a decimator 15. The decimator 15 selects only some of the samples input thereto and discards the remainder, outputting data at a rate of
      R    sample    =            U      D        ⁢                  R        symbol            .      The decimation factor D is an integer because the decimator 15 selects a fixed number of samples from each of the data samples within a symbol period. This traditional approach restricts the sample rate to always be related to the symbol by an integer factor U, such that Rsample=URsymbol. This restriction may be acceptable in modems with a limited set of symbol-rate requirements, particularly if the set of symbol rates are related by an integer factor. In highly flexible modem designs with a large set of non-integer related symbol rates, this traditional approach would impose difficulties in the design of corresponding digital-to-analog conversion and the analog reconstruction filter that follows (i.e., mixed-signal and analog design). Specifically, the digital-to-analog converter clocked at the clock rate would have to satisfy all possible cases of sample rates. The analog reconstruction filter generally has a cut-off frequency equal to one half the sample rate, which would impose additional error when the sample rate changes dramatically with respect to the symbol rate.
Traditional fractional interpolation using upsampling and decimation imposes additional hardware requirements, is computationally expensive, and the necessary division operation imposes a timing jitter that tends to accumulate absent an additional control loop. For example, to increase a sampling rate from 10 million samples per second (msps) to 15 msps, prior art approaches teach interpolating by the integer factor U=3 to produce an intermediate sampling rate of 30 msps, followed by decimating by the integer factor D=2 to yield the desired 15 msps
      (                  10        ⁢                                  ⁢        msps        ×                  3          2                    =              15        ⁢                                  ⁢        msps              )    .Assuming a desired sample rate of 16 msps from a sample rate of 10 msps, upsampling by a factor U=8 is required to achieve an intermediate sample rate of 80 msps, followed by decimation by the integer factor D=5 to yield the desired sample rate of 16 msps
      (                  10        ⁢                                  ⁢        msps        ×                  8          5                    =              16        ⁢                                  ⁢        msps              )    .Upsampling and decimation thus requires hardware that must process a very high intermediate sample rates. The intermediate sample rate is often the limiting criterion in data transfer speeds, but is itself merely a means to the final sample rate ends. Also, interpolation by a very large factor is required to achieve reasonable accuracy, and filtering must be done on the very high intermediate sampling rate. Therefore, interpolation by upsampling and decimation is generally not practical with field programmable gate arrays (FPGA), digital signal processors, or general-purpose processors, which each form the basis of programmable modems and software-defined radios.
Fractional interpolation is an alternative to the above approach, and refers to a delay from the symbol edge that is not necessarily an integer multiple of the sample interval (presuming uniform sampling, though that is not a limitation to the invention herein). Fractional interpolation enables the ratio of the timing instant to the symbol time to be irrational, which it will be in practically all cases wherein the symbol timing derives from a source (i.e., the system clock) independent of the sample clock. Even assuming the very high intermediate symbol rates as described above, prior art interpolation/decimation approaches only approximate an exact timing instant that true fractional interpolation can yield. That is to say, if an ideal sample time within a symbol period is an integer U plus a fraction χ of the integer, the prior art approach described above yields an approximation of that time as
  U  Dsuch that
            U      D        ≅          χ      ⁢                          ⁢      U        ,but the prior art approach will exactly yield the ideal sample time only by happenstance.
As can be appreciated, fractional interpolators can be more complex to implement than integer sampling. Prior to this invention, fractional interpolation was limited in speed (sampling rate) and furthermore was limited in an ability to operate at the system's symbol rate. The present invention as described below improves over the above prior art approach.